ABEOINTEN=DISABLE_END_OF_AUTO_, ABTOINTEN=DISABLE_AUTO_BAUD_TI, RXIE=DISABLE_THE_RX_LINE_, THREIE=DISABLE_THE_THRE_INT, RBRIE=DISABLE_THE_RDA_INTE
Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0).
| RBRIE | RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt. 0 (DISABLE_THE_RDA_INTE): Disable the RDA interrupts. 1 (ENABLE_THE_RDA_INTER): Enable the RDA interrupts. |
| THREIE | THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5]. 0 (DISABLE_THE_THRE_INT): Disable the THRE interrupts. 1 (ENABLE_THE_THRE_INTE): Enable the THRE interrupts. |
| RXIE | RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1]. 0 (DISABLE_THE_RX_LINE_): Disable the RX line status interrupts. 1 (ENABLE_THE_RX_LINE_S): Enable the RX line status interrupts. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |
| ABEOINTEN | Enables the end of auto-baud interrupt. 0 (DISABLE_END_OF_AUTO_): Disable end of auto-baud Interrupt. 1 (ENABLE_END_OF_AUTO_B): Enable end of auto-baud Interrupt. |
| ABTOINTEN | Enables the auto-baud time-out interrupt. 0 (DISABLE_AUTO_BAUD_TI): Disable auto-baud time-out Interrupt. 1 (ENABLE_AUTO_BAUD_TIM): Enable auto-baud time-out Interrupt. |
| RESERVED | Reserved. Read value is undefined, only zero should be written. |